1. Technical Field
Embodiments of the present inventions relate in general to throttling commands to integrated circuit chips.
2. Background Art
Semiconductor chips can malfunction if they get too hot. The temperature of a chip (also called a die) is related the number of operations of the chip performs per unit time. To keep chips from running too hot, the number of operations of the chips can be restricted either in response to an actual temperature measurement, or based on a predetermined number of operations. This is referred to as throttling. Some operations have much more power intensive than others. In some systems, throttling involves some commands such as read and write transactions (“reads” and “writes” or “activations”) involving other chips, but not other commands such as sync pulses and refresh. In the case in which throttling involves an actual temperature measurement, if the measured temperature is above a particular amount, the number of transactions can be restricted until the temperature is below a particular amount, which may be lower than the temperature which triggered the throttling to prevent rapid switching between throttling and not throttling. In the case in which throttling involves a predetermined number of operations, the number of operations in a window of time is prevented from exceeding the predetermined number.
Memory systems have been used in these types of throttling. In particular, the memory controller reduces the number of read and write transactions or stops the transactions altogether for either the window of time or until the temperature is sufficiently reduced.
Various arrangements for memory chips in a memory system have been proposed. For example, in a traditional synchronous dynamic random access memory (DRAM) system, memory chips communicate data through bidirectional data buses and receive commands and addresses through command and addresses buses. The memory chips have stubs that connect to the buses. Other memory systems use unidirectional signaling. Some memory systems use a multi-drop signaling arrangement in which signals are transmitted to more than one receiver. Other memory systems use point-to-point signaling in which signals are transmitted to only one receiver.
A Fully-Buffered Dual In-Line Memory Module (FBD or FBDIMM) system includes a memory module having a buffer and memory chips on one or both sides of a substrate. In traditional DRAM systems, read and write commands and the read and write data are passed directly between the memory controller and the memory chips. By contrast, with an FBD system, read and write commands and the read and write data are passed between the memory controller and a buffer, and between a buffer and the memory chips. There is a narrow high speed channel between the memory controller and the buffer, and a more traditional bus between the buffer and the memory chips. However, narrow high speed interconnects between the buffer and memory chips has been proposed. There may be more than one memory module in series, with the buffer of one module communicating with the buffer of another module. There may also be more than one buffer on a module. Further, some systems have more than one parallel channel between the memory controller and different modules.
In FBD systems, command, address, and write data signals are provided in frames between the memory controller and the buffer and between the buffer and the memory chips. In the buffer, the frames are one clock period in duration with several parallel conductors. Read data is provided in the opposite direction from the memory chips to the buffer and from the buffer to the memory controller. In some FBD systems, a sync frame (or sync pulse) is provided by the memory controller to the buffer every 42 clock periods. In response to the sync frame, the buffer provides a status frame (or status pulse) which includes status bits.
Current memory controller traffic-throttling algorithms either do not turn off clock-enables while they are prohibiting memory transactions (desktops and servers), or they turn off clock-enables aggressively as a means of prohibiting memory transactions (mobile systems).
In some memory systems, a memory chip receives signals and repeats them to a next memory chip in a series of two or more memory chips. In some of these systems, the last memory chip in the series can send a signal directly back to a memory controller. This is referred to as a ring. In some such systems, a memory chip provides some read data signals while also providing commands to another memory chip which provides additional read data signals. Unidirectional lanes have been used to carry packetized command, address, and write data signals, along with clocks signals, between memory controllers and memory chips, and between memory chips. The signals carrying write data may be separate from the signals carrying command and address signals. Status bits may be carried with the read data.
In some memory systems, all the memory chips are on memory module substrates. In other memory systems, some of the chips may be “down” on the motherboard and other memory chips may be “up” on the memory module.
Power consumption, cost, delivered bandwidth, reliability, availability, and serviceability (RAS) are some of the issues to address on the chip systems in general, including FBD technology.
Some memory controllers are included in processor chips that include one or more processor cores. The processor chips are coupled to an input/output controller. Other memory controllers are included in memory controller hubs that are coupled to an input/output controller. In some memory systems, there are multiple concurrent channels between the chip including the memory controller and other portions of a computer system. In some implementations, the input/output controllers may be coupled to wireless transmitting and receiving circuitry.